The paradigm shift toward multi-core architectures in embedded systems has introduced significant challenges regarding temporal predictability and resource isolation. As modern applications in automotive, aerospace, and industrial automation demand higher computational throughput, the integration of mixed-criticality tasks onto a single hardware platform becomes a necessity. This article explores the intricate relationship between virtualization technologies, memory hierarchy management, and real-time performance. We investigate the influence of hypervisors on embedded system performance, specifically focusing on the trade-offs between hardware abstraction and deterministic execution. The research provides an extensive theoretical elaboration on the role of formal verification in OS kernels, such as seL4, and the deployment of real-time Linux for industrial platforms. Furthermore, we analyze advanced memory scheduling infrastructures, including DRAM controllers designed for mixed-criticality and re-programmable logic interfaces. A central component of this study is the evaluation of fault-tolerant architectures, specifically the dual-core lockstep mechanism for zonal controllers, and how these hardware-level safety features interact with virtualized environments. By synthesizing current methodologies in cache management, bus arbitration, and task isolation, this paper establishes a comprehensive framework for achieving determinism in complex multi-core environments. The results demonstrate that while virtualization introduces inherent overhead, strategic memory partitioning and hardware-assisted isolation can mitigate interference, ensuring that high-criticality tasks meet their deadlines even under heavy synthetic stress.

Multi-core Embedded Systems, Deterministic Virtualization, Real-Time Hypervisors, Memory Hierarchy

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